1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device with field-shield isolation structure and a method for manufacturing the same.
2. Description of the Background Art
FIG. 44 is a plan view of a background-art semiconductor device with field-shield isolation structure. In this figure, defining an active region AR of a MOS transistor, a field-shield (FS) gate electrode 1 is formed like a rectangular ring to make a field-shield isolation structure and a gate electrode 2 of the MOS transistor is formed above the FS gate electrode 1 so as to halve the FS gate electrode 1.
The active regions AR externally located on both sides of the gate electrode 2 are regions to serve as source/drain (S/D) regions 3 and above the S/D regions 3, S/D electrodes 4 mainly made of aluminum are formed. A plurality of contact holes 5 are formed between the S/D regions 3 and the S/D electrodes 4.
Further, insulating layers are provided between the FS gate electrode 1 and the gate electrode 2 and between the S/D region 3 and the S/D electrode 4, but not shown in this figure, for convenience of illustration, to allow main elements to be clearly seen.
FIG. 45 is a cross section taken along the lines A--A of FIG. 44, showing a construction of the MOS transistor and the FS gate electrode formed on a bulk silicon substrate.
In this figure, the gate electrode 2 is formed on a surface of a silicon substrate SB. The gate electrode 2 has a gate oxide film 21 formed on the surface of the silicon substrate SB, a polysilicon layer 22 formed on the gate oxide film 21 and a salicide layer 23 formed on the polysilicon layer 22, and side wall oxide films 24 are formed on the side surfaces of these film and layers. In the surface of the silicon substrate SB outside each side of the gate electrode 2, an S/D layer 31 and a lightly doped drain (LDD) layer 32 which constitute the S/D region 3 are provided. A salicide layer 33 covers the surface of the S/D layer 31.
On the surface of the silicon substrate SB outside the S/D region 3, the FS gate electrode 1 is formed. The FS gate electrode 1 has an FS gate oxide film 11 formed on the surface of the silicon substrate SB, a polysilicon layer 12 formed on the FS gate oxide film 11 and an FS upper oxide film 13 formed on the polysilicon 15 layer 12, and side wall oxide films 14 are formed on the side surfaces of these films and layer. Furthermore, in some cases, the construction of the FS gate electrode 1 is referred to as a field-shield isolation structure and the polysilicon layer 12 is referred to as an FS gate electrode.
An interlayer insulating film 9 is formed so as to cover the FS gate electrode 1, the gate electrode 2 and the S/D region 3. A contact hole 5 is formed, penetrating the interlayer insulating film 9 between the S/D region 3 and the S/D electrode 4 and filled with conductor, to thereby electrically connect the S/D region 3 and the S/D electrode 4 to each other.
Next, with reference to FIGS. 46 to 51, a manufacturing process will be discussed. First, the FS gate oxide film 11, the polysilicon layer 12 and the FS upper oxide film 13 are layered on the silicon substrate SB (implanted with channel) in this order. With a resist mask R1, a patterning is performed on the multiple layers as shown in FIG. 46, to form the FS gate electrode 1. The FS gate oxide film 11 is formed by CVD (=Chemical Vapor Deposition) at the temperature of 700.degree. C. to have a thickness of 100 to 1000 .ANG.. The polysilicon layer 12 is formed by CVD at the temperature of 600 to 800.degree. C. to have a thickness of 100 to 1000 .ANG.. The polysilicon layer 12 is implanted with phosphorus (P) of about 1.times.10.sup.20 /cm.sup.3 as impurity. The FS upper oxide film 13 is formed by CVD, for example, at the temperature of 700.degree. C. to have a thickness of 500 to 2000 .ANG..
In the step of FIG. 47, after removing the resist mask R1, the side wall oxide film 14 is formed. The process for forming the side wall oxide film 14 is as follows: an oxide film is formed so as to cover the FS gate electrode 1 and then the oxide film is selectively removed by anisotropic etching (dry etching), to form the side wall oxide film 14 being self-aligned. In this case, however, there is a problem of damage due to the anisotropic etching left at a region X on the surface of the silicon substrate SB in FIG. 47. This problem will be discussed later in detail with reference to FIGS. 56 and 57.
Subsequently, the gate oxide film 21 is formed on the surface of the silicon substrate SB and the polysilicon layer 22 is formed so as to cover the gate oxide film 21 and the FS gate electrode 1. Then, as shown in FIG. 48, a resist mask R2 is formed at a predetermined position on the polysilicon layer 22 and a patterning is performed on the polysilicon layer 22 through the resist mask R2.
In the step of FIG. 49, with the polysilicon layer 22 used as a mask, the LDD layer 32 is formed, being self-aligned, by ion implantation. In this ion implantation, arsenic (As) or phosphorus (P) is injected at an energy of 30 to 70 KeV at a dose of 1.times.10.sup.13 to 4.times.10.sup.14 /cm.sup.2. The ion injection should be continuously performed at an injection angle of 45.degree. to 60.degree., with the silicon substrate rotated.
Subsequently, as shown in FIG. 50, the side wall oxide film 24 is formed on the side wall of the gate electrode 2. The process for forming the side wall oxide film 24 is as follows: an oxide film having a thickness of 500 to 800 .ANG. is formed so as to cover the gate electrode 2 and then the oxide film is selectively removed by anisotropic etching (dry etching), to form the side wall oxide film 24 being self-aligned.
After that, with the FS gate electrode 1 and the gate electrode 2 used as a mask, the S/D layer 31 is formed by ion implantation. In this ion implantation, arsenic (As) or phosphorus (P) is injected at an energy of 30 to 70 KeV at a dose of 4.times.10.sup.14 to 7.times.10.sup.15 /cm.sup.2.
Subsequently, as shown in FIG. 51, the salicide films 23 and 33 are formed, being self-aligned, only on the upper surface of the gate electrode 2 and the surface of the S/D region 3. These salicide films 23 and 33 may be any of cobalt silicide, titanium silicide, tungsten silicide or the like.
After that, the interlayer insulating film 9 is formed so as to cover the FS gate electrode 1, the gate electrode 2 and S/D region 3, the contact hole 5 is formed so as to penetrate the interlayer insulating film 9 on the S/D region 3 and filled with the conductor, and the S/D electrode 4 mainly made of aluminum is formed thereon, to obtain the background-art semiconductor device with field-shield isolation structure as shown in FIGS. 44 and 45.
Next, a cross section taken along the lines B--B of FIG. 44 is shown in FIG. 52. In this figure, the gate oxide film 21 is formed on the surface of the silicon substrate SB between two FS gate electrodes 1, and the polysilicon layer 22 is formed so as to cover the gate oxide film 21 and the FS gate electrodes 1. Further, the salicide film 23 is formed on the polysilicon layer 22. Furthermore, in the silicon substrate SB beneath the gate oxide film 21, a channel region is created when the device operates.
The interlayer insulating film 9 is formed so as to cover the FS gate electrode 1, the gate electrode 2 and the S/D region 3, and the contact hole 5 is formed so as to penetrate the interlayer insulating film 9 located on the end portion of the gate electrode 2 and filled with the conductor, to connect the gate electrode 2 and a gate interconnection layer 6.
A manufacturing process will be discussed below with reference to FIGS. 53 to 55. First, the FS gate oxide film (field-shield oxide film) 11, the polysilicon layer 12 and the FS upper oxide film 13 are layered on the silicon substrate SB in this order. With the resist mask R1, a patterning is performed on the multiple layers as shown in FIG. 53, to form the FS gate electrode 1. This step is the same as that of FIG. 46, so redundant discussion is omitted.
In the step of FIG. 54, after removing the resist mask R1, the side wall oxide film 14 is formed. The process for forming the side wall oxide film 14 is as follows: an oxide film is formed so as to cover the FS gate electrode 1 and then the oxide film is selectively removed by anisotropic etching (dry etching), to form the side wall oxide film 14 being self-aligned.
In this step, the damage due to the anisotropic etching is left at a region Y on the surface of the silicon substrate SB in FIG. 54. This damage is the same as that at the region X of FIG. 47. This problem will be discussed later in detail with reference to FIGS. 56 and 57.
Subsequently, in the step of FIG. 55, the gate oxide film 21 is formed on the surface of the silicon substrate SB, and the polysilicon layer 22 which is a body of the gate electrode 2 is formed so as to cover the gate oxide film 21 and the FS gate electrode 1. This step for forming the polysilicon layer 22 is the same as that of FIG. 48, so redundant discussion is omitted. In this case, a defect is caused at a region Z of FIG. 55 by the damage at the region Y on the surface of the silicon substrate SB in FIG. 54. This problem will be discussed later in detail with reference to FIG. 58.
Then, as discussed with reference to FIG. 51, the salicide films 23 and 33 (not shown) are formed, being self-aligned, only on the upper surface of the gate electrode 2 and the surface of the S/D region 3 (not shown). The interlayer insulating film 9 is formed so as to cover the FS gate electrode 1 and the gate electrode 2, and the contact hole 5 is formed so as to penetrate the interlayer insulating film 9 located on the end portion of the gate electrode 2 and filled with the conductor, and the gate interconnection layer 6 mainly made of aluminum is formed thereon, to obtain the background-art semiconductor device with field-shield isolation structure as shown in FIGS. 44 and 45.
The following prior-art documents on the field-shield gate have been found by searching. Outlines thereof will be presented below.
In Japanese Patent Application Laid Open Gazette 7-273185 disclosing a construction intended to avoid bloating of end portions of a shield gate oxide film, no description is found on any construction in which a surface of a semiconductor substrate on which a MOS transistor is formed is located lower than a surface of the semiconductor substrate on which a field-shield oxide film is formed and its action and effect.
In Japanese Patent Application Laid Open Gazettes 2-137335 and 6-204237 disclosing a construction in which end portions of a gate oxide film are thicker, no reference is made to the thickness of edge portions of a field-shield oxide film, and no description is found on any construction in which a surface of a semiconductor substrate on which a MOS transistor is formed is located lower than a surface of the semiconductor substrate on which the field-shield oxide film is formed and its action and effect.
In Japanese Patent Application Laid Open Gazettes 56-104446 and 57-36842 disclosing a construction in which a semiconductor layer for isolation has higher impurity concentration, no reference is made to the problems inherent in the SOI (Silicon-On-Insulator) substrate, and no description is found on any construction in which a surface of a semiconductor substrate on which a MOS transistor is formed is located lower than a surface of the semiconductor substrate on which a field-shield oxide film is formed and its action and effect of lowering the electric resistance of an SOI layer beneath a field-shield gate electrode.
Having the above construction and manufactured by the above method, the background-art semiconductor device with field-shield isolation structure has the following problem.
FIG. 56 illustrates the structure at the region X of FIG. 47 and the region Y of FIG. 54 in detail. In this figure shown is a state immediately after the side wall oxide film 14 is formed on the side surface of the FS gate electrode 1 by anisotropic etching (dry etching).
When the side wall oxide film 14 is formed, for excellent directivity in anisotropic etching, dry etching is adopted, which may cause overetching that removes the surface of the silicon substrate SB.
Especially, at an edge portion of the side wall oxide film 14, more silicon is removed than at other portions and as a result the silicon substrate SB is partially scooped out. One of the factors that cause this phenomenon is locally-unequal density of an etchant. Thus, a dent portion DP is created on the surface of the silicon substrate SB near the edge portion of the side wall oxide film 14 as shown in FIG. 56.
After the step of forming the side wall oxide film 14, a natural oxide film formed on the surface of the silicon substrate SB must be removed by wet etching prior to forming the gate oxide film 21 on the surface of the silicon substrate SB as discussed with reference to FIG. 48. At this time, together with the natural oxide film, the FS upper oxide film 13 and the side wall oxide film 14 are slightly removed. This state is shown in FIG. 57.
In this figure, the broken line indicates where the FS upper oxide film 13 and the side wall oxide film 14 were formed before removing the natural oxide film. As is clear from FIG. 57, an edge portion EP is created in the periphery of the side wall oxide film 14 as the FS upper oxide film 13 and the side wall oxide film 14 are retracted.
FIG. 58 shows a state after forming the gate oxide film 21 and the polysilicon layer 22 in this condition. This figure is a detailed view of the region Z of FIG. 55.
As shown in FIG. 58, the gate oxide film 21 is formed over the edge portion EP. The gate oxide film 21 is thin, having a thickness of about 50 to 100 .ANG., and in some cases, that on the edge portion EP is thinner. Further, at the edge portion EP, electric field is more intense due to electric field concentration. This, along with thinness of the gate oxide film 21, may cause breaking of the gate oxide film 21 with high possibility.
That results in less reliability of the gate oxide film and by extension, of the MOS transistor with field-shield isolation structure.
Furthermore, the MOS transistor with field-shield isolation structure on an SOI substrate has the same problem.
Though the brief discussion has been made, in the SOI substrate or the bulk silicon substrate, channel injection is performed before forming the S/D layer and the LDD layer. In the channel injection, the background-art method has the following problem. The problem in the channel injection will be discussed below with reference to FIGS. 59 to 64, taking a process for manufacturing a CMOS transistor with field-shield isolation structure on the SOI substrate as an example.
As shown in FIG. 59, the FS gate electrode 1 is formed on the SOI substrate OB, and the SOI substrate OB is separated into the NMOS transistor formation region NR and the PMOS transistor formation region PR. At this time, a mask alignment mark AL of the same configuration as the FS gate electrode 1 is also formed. Further, the SOI substrate OB consists of the insulating substrate including the silicon substrate SB and the buried oxide layer OX formed thereon, and the SOI layer (single crystalline silicon layer) SL formed on the insulating substrate.
Furthermore, as discussed earlier, there arises a problem that with formation of the FS gate electrode 1, the SOI layer SL is scooped out near the edge portion of the side wall oxide film 14.
Next, in the step of FIG. 60, a resist mask R3 is formed in the NMOS transistor formation region NR, and a channel is injected into the PMOS transistor formation region PR to form a channel injection region CDP. This injection is performed with phosphorus ion, for example.
Subsequently, in the step of FIG. 61, a resist mask R4 is formed in the PMOS transistor formation region PR, and a channel is injected into the NMOS transistor formation region NR to form a channel injection region CDN. This injection is performed with boron ion, for example. The mask alignment mark AL is used to align the positions for forming the resist masks R3 and R4.
The state after the channel injection near the FS gate electrode 1 is shown in FIG. 62. The injected impurity (P or B) has an injection peak at the position indicated by the broken line IP, as shown in FIG. 62. Specifically, the impurity has the injection peak at the middle position in the SOI layer SL on which no FS gate electrode 1 is formed and has the peak inside the polysilicon layer 12 in the FS gate electrode 1. This distribution is caused by the injection at an energy suitable for the SOI layer SL. To inject the channel also into the SOI layer SL beneath the FS gate electrode 1, it is necessary to perform the ion injection at higher energy. The state after this injection is shown in FIG. 63.
As indicated by the broken line IP of FIG. 63, the injected impurity (P or B) has an injection peak in the SOI layer SL beneath the FS gate electrode 1 and in the buried oxide layer OX of the insulating substrate on which no FS gate electrode 1 is formed.
The channel injection region obtained by the above two ion injection is shown in FIG. 64. As shown in FIG. 64, channel injection regions CD1 and CD2 each having an almost-desired concentration are formed in the SOI layer SL on which no FS gate electrode 1 is formed and in the SOI layer SL beneath the FS gage electrode 1, respectively, but the impurity in the SOI layer SL beneath the side wall oxide film 14 does not have the desired concentration.
Thus, since the channel injection is performed after forming the FS gate electrode 1 in the background art, the channel has to go through the FS gate electrode 1 at higher energy if it is required that the channel should be injected also into the semiconductor layer beneath the FS gate electrode 1. Therefore, when the SOI substrate OB is used, there is a possibility that the impurity may be injected also into the buried oxide layer OX in the portion where no FS gate electrode 1 is formed, and on the other hand, the impurity beneath the side wall oxide film 14 of the FS gate electrode 1 can not have the desired concentration.